The present invention relates to the manufacture of semiconductor devices and, more particularly, to a method of forming a structure with buried regions in a semiconductor device.
In the design of integrated circuits, there is often a need to produce components having different electrical characteristics, for example, power transistors, diodes with high reverse-breakdown voltages, signal transistors for signal-processing units and control units. There is a particular need for very good insulation from the substrate, particularly for components of some types, to prevent parasitic currents and interference with the operation of the integrated circuit. For these components, it is often very helpful to use techniques that enable insulating layers of dielectric material to be formed. One of these techniques is based on the use of SOI (silicon on insulator) wafers, that is, composite wafers constituted by two layers of silicon, one thicker layer which acts as a support and one thinner layer in which the components of the integrated circuit are formed, the layers being separated by a layer of silicon dioxide. For other components, for example, power transistors with vertical conduction, it is necessary to use a wafer constituted by a substrate of monocrystalline silicon covered by a thin silicon layer produced by epitaxial growth.
A method of manufacturing SOI wafers is the subject of European patent application 98830007.5 filed on Jan. 13, 1998, in the name of SGS-Thomson Microelectronics S.r.l, and which is incorporated in its entirety herein by reference. The main steps of this method are common to the method of the present invention and will therefore be described below in the course of the description of an embodiment of the invention. This known method was designed to be used mainly to produce an SOI structure that extends throughout the wafer but may also be used to produce an SOI structure on only a portion of the wafer. It is therefore suitable for the production of integrated circuits comprising both power components with vertical conduction and components with good insulation, that is, with practically zero leakage currents to the substrate.
A component with good insulation that can be produced by this method is shown in FIG. 1. In particular, FIG. 1 shows, in section, a portion of a wafer containing a diode.
The wafer comprises a substrate 10 of monocrystalline silicon with p-type conductivity and an epitaxial layer 11 formed on the substrate 10. A silicon dioxide plaque 12 separates a portion of the epitaxial layer 11 from the substrate. A diffused planar region 13 with p-type conductivity and with low resistivity (and hence indicated p+) extends from the front surface of the wafer as far as the oxide plaque 12 in the form of a ring or frame inside which an epitaxial region 11xe2x80x2 is defined. Two planar regions, that is, a p-type region 14 and an n-type region 15 with low resistivity (and hence indicated n+) are formed in this epitaxial region and each has, on the surface, a contact electrode with the function of an anode terminal A and of a cathode terminal K of the diode, respectively. The diode is insulated from the substrate 10 very effectively but has a considerable resistance when it is biased for direct conduction because of the relatively high resistivity of the epitaxial region 11xe2x80x2.
A usual method of reducing this resistance is to form a buried n-type layer of low resistivity by implantation of a high dose of doping ions before the growth of the epitaxial layer. With the known method, however, the growth of the epitaxial layer on the portion of the wafer in which the oxide plaque has been formed takes place on a discontinuous surface partly of silicon and partly of oxide so that it is a critical operation per se (this processing step according to the known method will also be described below since it is common to the known method and the method according to the invention). Implantation at this point would not be advisable because it would lead to unacceptable contamination of the oxide of the plaque 12 or would require masking operations which would complicate the method considerably.
The embodiment of the present invention is directed to a method by which it is possible to form integrated circuits comprising components of different types including components that are completely insulated from the substrate and which have a low resistance during direct conduction.
A particular aspect of the embodiment of the present invention is a method that enables high-performance devices with dielectric insulation and buried regions to be formed.
These objects are achieved by a method for forming a semiconductor device on a monocrystalline silicon substrate that includes forming a planar region of a predetermined depth to have a first conductivity type in the monocrystalline silicon substrate; etching the planar region and the monocrystalline silicon substrate to form trenches through the planar region and into the monocrystalline silicon substrate; transforming regions in the monocrystalline silicon substrate below the planar region and between the trenches into silicon dioxide to form a silicon dioxide plaque; and forming a buried region of the first conductivity type over the silicon dioxide plaque by subjecting the monocrystalline silicon substrate to epitaxial growth to fill in the trenches and distribute doping impurities to achieve homogeneous resistivity throughout the buried region.
In accordance with another aspect of the present invention, a method for forming a structure with a buried region in a semiconductor device having the following steps is provided: Introducing doping impurities into a monocrystalline silicon substrate through a portion of a flat major surface of the substrate to a predetermined depth to form a planar region having a first type of conductivity; subjecting the substrate to selective anisotropic etching to form trenches in the substrate from the portion of the major surface to a depth greater than the predetermined depth; oxidizing the silicon within the trenches starting a predetermined distance from the major surface of the substrate until the portions of the substrate between the adjacent trenches are transformed into silicon dioxide and until the trenches are filled with silicon dioxide below a level defined by the predetermined distance in order to form a silicon dioxide plaque; and subjecting the substrate to a treatment of epitaxial growth from a vapor phase, the operative parameter selected in a manner to permit a growth of monocrystalline silicon inside the portions of the trenches that are still open until the trenches are closed and on top of the major surface of the substrate in a manner to permit a redistribution of the doping impurities into the monocrystalline silicon grown and to form a region with the first type of conductivity having substantially homogeneous resistivity buried in an epitaxial layer and extending on the silicon dioxide plaque.